How many IP21 writes to a REMSET block can a MFP02 handle before NVM Overuns occur & how many can a BRC410 handle?
I believe that I have a NVM Overrun error on a MFP02 due to too many IP21 writes into REMSET blocks? They are redundant MFP controllers.
I am wondering if upgrading to a BRC410 would solve the problem?
I am wondering if upgrading to a BRC410 would solve the problem?
Asked 11 months ago
Voted best answer
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Hi,
The MFPxx series of controllers (and the BRC100/200 from memory) have a limit of 20 writes per second and the BRC300/400/410 limit was lifted to 80 writes per second from revision L firmware onwards. Replacing the MFPs with BRC410s would lift the NVRAM write limit.
The following table is snipped from 3BUA002205R0001 - Harmony/Symphony Plus: Controllers - Byte 11, bit 3. NVRAM overrun, and shows the function codes that can initiate NVRAM writes.
55 Hydraulic Servo During calibration
62 Remote Control Memory When “Red-tagged”
68 Remote Manual Set Constant When the output value is changed by a command request (GMI) updating S4
80 Control Station
- When station mode is changed
- When set point is changed via a command request (GMI)
- When computer status is changed
- When “Red-tagged”
117 Boolean Recipe Table When Batch edits are executed
118 Real Recipe Table When Batch edits are executed
123 Device Driver When “Red-tagged”
129 Multi-State Device Driver When “Red-tagged”
136 Remote Motor Control When “Red-tagged”
140 Restore (1) On “Save” trigger
150 Hydraulic Servo Slave During Calibration
153 ISC Parameter Converter During self tune
154 Adaptive Parameter Scheduler During self tune
155 Regression During self tune
177 Data Acquisition Analog
- When mode is changed
- When “Red-tagged”
194 User Defined Data Export When “Red-tagged”
210 Sequence of events slave When “Red-tagged”
211 Data Acquisition Digital
- When mode is changed
- When “Red-tagged”
217 Enhanced Calibration Command During Calibration
Looking the table above and depending on the configuration in question it could be things other than IP21 RMSC writes that are actually setting the RNO bit. Often, Recipe and Restore blocks, either executing every cycle or periodically but all at the same time can contribute to regular RNO bit setting. Configuration that changes modes of multiple controllers at the same time is also a cause of intermittent RNO bit setting.
If the issue is with excessive writes from IP21, one solution is to not write into the RMSCs directly but configure the writes as AO/Ls in the IP21 ICI itself. These AO/Ls then become exception report traffic rather than GMI messages, which is what is causing the excessive NVRAM writes. As well as change the IP21 configuration, you would need to add AI/L / AI/I to the destination modules and then connect these into the logic. These inputs can still pass through the RMSCs but set the RMSC to track, say on IP21 signal quality and this will not trigger NVRAM writes.
Another possible issue with 3rd party hosts writing into controllers can be a lack of significant change for the writes which causes continual writes to the RMSC / STATION even though the value is only changing by tiny amounts. This can then contribute unnecessarily to the load on NVRAM write capacity of the controller. Configuring the IP21 writes as AO/Ls also provides access to the significant change spec for the AO/L.
Regards,
Alan
The MFPxx series of controllers (and the BRC100/200 from memory) have a limit of 20 writes per second and the BRC300/400/410 limit was lifted to 80 writes per second from revision L firmware onwards. Replacing the MFPs with BRC410s would lift the NVRAM write limit.
The following table is snipped from 3BUA002205R0001 - Harmony/Symphony Plus: Controllers - Byte 11, bit 3. NVRAM overrun, and shows the function codes that can initiate NVRAM writes.
55 Hydraulic Servo During calibration
62 Remote Control Memory When “Red-tagged”
68 Remote Manual Set Constant When the output value is changed by a command request (GMI) updating S4
80 Control Station
- When station mode is changed
- When set point is changed via a command request (GMI)
- When computer status is changed
- When “Red-tagged”
117 Boolean Recipe Table When Batch edits are executed
118 Real Recipe Table When Batch edits are executed
123 Device Driver When “Red-tagged”
129 Multi-State Device Driver When “Red-tagged”
136 Remote Motor Control When “Red-tagged”
140 Restore (1) On “Save” trigger
150 Hydraulic Servo Slave During Calibration
153 ISC Parameter Converter During self tune
154 Adaptive Parameter Scheduler During self tune
155 Regression During self tune
177 Data Acquisition Analog
- When mode is changed
- When “Red-tagged”
194 User Defined Data Export When “Red-tagged”
210 Sequence of events slave When “Red-tagged”
211 Data Acquisition Digital
- When mode is changed
- When “Red-tagged”
217 Enhanced Calibration Command During Calibration
Looking the table above and depending on the configuration in question it could be things other than IP21 RMSC writes that are actually setting the RNO bit. Often, Recipe and Restore blocks, either executing every cycle or periodically but all at the same time can contribute to regular RNO bit setting. Configuration that changes modes of multiple controllers at the same time is also a cause of intermittent RNO bit setting.
If the issue is with excessive writes from IP21, one solution is to not write into the RMSCs directly but configure the writes as AO/Ls in the IP21 ICI itself. These AO/Ls then become exception report traffic rather than GMI messages, which is what is causing the excessive NVRAM writes. As well as change the IP21 configuration, you would need to add AI/L / AI/I to the destination modules and then connect these into the logic. These inputs can still pass through the RMSCs but set the RMSC to track, say on IP21 signal quality and this will not trigger NVRAM writes.
Another possible issue with 3rd party hosts writing into controllers can be a lack of significant change for the writes which causes continual writes to the RMSC / STATION even though the value is only changing by tiny amounts. This can then contribute unnecessarily to the load on NVRAM write capacity of the controller. Configuring the IP21 writes as AO/Ls also provides access to the significant change spec for the AO/L.
Regards,
Alan
Answered 11 months ago
Source: 3BUA002205R0001
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